FIG. 1 illustrates a cross section view of a conventional Vertical DMOS (VDMOS) device 10. The VDMOS device 10 achieves high drain voltage without rupturing the gate ox in a subtle way. As the drain voltage increases, the depletion regions of adjacent active areas take the highest portion of this voltage as opposed to the gate oxide. This spread out of the depletion region from the adjacent DMOS bodies into the Nwell or N type epitaxial regions absorbs most of the voltage. When the depletion regions merge, no further voltage is applied to the gate oxide.
This approach results in an output transfer curve as shown in FIG. 2. Note that this curve is made up of three sections: (A) linear portion, (B) quasi saturated or pinched-off portion and (C) the saturated portion. Portions A and C are ideal but the B portion represents an unwanted condition. This quasi saturated portion is a high resistance region that is not saturated as the ideal section C represents. This quasi saturated region is the result of current flow down the funnel region 16 shown in FIG. 1 and marked Fet. Current flow down this funnel region 16 results in a pinched-off region (B) forming as the current flow increases, much like a normal FET device. As the current flow increases, it produces a voltage drop which results in a depletion region which tends to pinch off this funnel. This pinched-off region increases until it completely pinches off and represents the saturated condition. This results in the increase in resistance of the funnel region 16.
Accordingly, what is needed is a device that overcomes the above-identified problems. The present invention addresses such a need.